1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, relates to a static RAM (SRAM).
2. Description of the Related Art
In recent years, the size of transistors constituting a memory cell and the like has been reduced for improvement in integration density of semiconductor memory devices. In addition, along with lowering of supply voltage, the threshold voltage of such transistors has also been lowered. For these reasons, fluctuation in the threshold voltage of the transistors constituting the memory cell has increasingly given a large influence on operation of the memory cell.
Particularly in the SRAMs, fluctuation in the threshold voltage of the transistors constituting the memory cell reduces a static noise margin (hereinafter, SNM) of the memory cell. A memory cell having a low SNM does not have stable operation. Therefore, when a weak voltage is applied from a bit line due to noise and the like, erroneous write to the memory cell occurs due to the weak voltage. For that reason, a transistor for data transfer (hereinafter, transfer transistor) is conducted to a memory cell connected to a word line to which a selected memory cell is connected (hereinafter, a non-selected memory cell). Accordingly, when the SNM is low, unnecessary writing occurs due to noise and the like transferred from the bit line.
In consequence, the SRAMs formed with a configuration known in the prior art have problems associated with lowering of the supply voltage and reduction of the transistor size.
As countermeasures against that, a method has been disclosed in which: the transfer transistor is formed of a FinFET; a gate of the transfer transistor is divided into a front gate and a back gate; and the back gate is connected to a storage node of a memory cell. Here, the FinFET has a structure in which: a channel part is formed on an insulating layer of a semiconductor substrate; and an upper surface and right and left side surfaces of the channel part are surrounded by a gate electrode with an insulating film therebetween. Since the channel part is covered with the insulating film and these surfaces of the channel part are controlled by the gates, leakage current when the device is OFF can be reduced.
With this method, since the back gate of one of the transfer gates is connected to a node that stores data of “L”, the back gate is at an “L” level. When the back gate is at the “L” level, the threshold voltage of the transistor is high. Thereby, the threshold voltage of the transfer transistor of a non-selected memory cell in which the back gate of the transfer transistor is at an “L” level is high enough to make it difficult to bring the transfer transistor of the non-selected memory cell into conduction. Therefore, erroneous write can be reduced.
On the other hand, this method has a problem that a reading speed and a writing speed are slow since a threshold voltage in the transfer gate of a selected memory cell is also high.
Consequently, in the prior art, it is difficult to provide a small-sized semiconductor memory device having high operational reliability.